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From Bob Helsel,
Editor, AXIe Newsletter

Welcome to the March 2015 issue of the AXIe Newsletter.

LinkedInOur AXIe Consortium LinkedIn membership numbers continue to increase and we are now a community of over 341 members. 

YoutubeIf you want to stay abreast of the AXIe standard you can subscribe to the new AXIe consortium YouTube Channel, or view the latest AXIe-0 Overview presentation on the website.

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AXIe Supports Cutting-Edge DDR Memory Design-Validation Solution

by Christopher Cain, Keysight Technologies

Dynamic memories (DDR) continue to become faster and wider with each iteration and the DDR4 standard was ratified by JEDEC in September 2012.   Design validation solutions for DDR memory designs require using lots of complex ASIC's and FPGA's to provide simultaneous read/write capability at greater than 3 Gb/s rates and scalable to as many bytes wide required.   AXIe was the right form-factor to formulate  a complex and scalable digital logic analyzer solution.

Richard Stern, Keysight Technologies R&D Manager states "The Keysight U4154B module contains a large number of high power custom ASICs, enabling it to be the only logic analyzer in the world to capture DDR4 and LPDDR4 data at 3.2Gb/s data rate.  The large board AXIe form factor allows for a coplanar design which preserves signal integrity, and also provides the power and cooling required by this complex module.  In addition, the two and five slot chassis allows us to easily scale the digital channel count of the measurement system up or down to solve a wide variety of customer challenges, from a single DRAM to a full DDR4 DIMM interposer solution."

Memory Trends: A Look Ahead
by Janine Love>>

AXIe Consortium Introduces
Wide PCI Express for AXIe

By Larry Desjardin, Modular Methods

This month, the AXIe Consortium released a specification named “Wide PCIe”, expanding the lane width, and associated data throughput, to or from an AXIe module.  Previously, all PCIe (PCI Express) fabrics were a maximum of four lanes wide.  Wide PCIe allows a module to support up to either 8 or 16 lanes of PCIe in each direction. Wide PCIe is a preliminary specification posted on the AXIe Consortium website in slide format.  It will be formally integrated into the next revision of the
AXIe-1 specification.

The “Wide PCIe” specification is straightforward.  The AXIe Consortium had previously reserved pins at each slot for expanding the PCIe lane width.  In the parlance of AXIe and AdvancedTCA, modules were only allowed to use Fabric Channel 1, a four-lane PCIe bus, but other fabric channels were reserved.  The new specification now allows Fiber Channels 2, 3, and 4 to transport data as well, allowing up to 16 lanes of transit in each direction.






New AXIe Products

The members of the AXIe Consortium continue to release a steady flow of new products based on the AXIe standard, some of which are spotlighted below:

AXIe-1 Base Architecture Specification Products

AXIe 65 GSa/s & 20 GHz High-Speed Arbitrary Waveform Generator

GT-ASG18A Advanced Signal Generator

M9521A AXIe System Module

M9514A AXIe 14-Slot Chassis


IPMI Shelf Manager Card With Redundant IPMB

M9703A AXIe eight-channel wideband digital receiver/digitizer

M8061A Multiplexer 2:1 With De-Emphasis 28 Gb/s

M8192A Multi-Channel Synchronization Module for M8190A

ADC 6000 Series AXIe-based Digitizer Module

DDR Logic Analyzer U4154A

AWG (Arbitrary Waveform Generator) M8190A

AXIe-3.1 Semiconductor Test Extension Products

AX500 - AXIe Benchtop System

High Volume Production Test System









Thanks to all our readers.
Bob Helsel, Editor


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